1. Field of the Invention
The present invention relates to a Bi-CMOS integrated circuit which monolithically integrates a vertical NPN bipolar transistor, a lateral PNP bipolar transistor, an N-channel MOS field effect transistor (referred to as N-MOSFET hereinafter) and a P-channel MOS field effect transistor (referred to as P-MOSFET hereinafter).
2. Description of the Prior Art
In a Bi-CMOS integrated circuit, bipolar transistors of a vertical doubly diffused NPN transistor and a lateral PNP transistor are formed on the same P type silicon substrate together with an N-MOSFET and a P-MOSFET.
A Bi-CMOS integrated circuit is equipped with both advantages of bipolar transistor's features presenting a high speed operability and large current drivability and the C-MOSFET's feature of the low power consumption.
In bipolar transistors, the structure and the fabrication process are designed with special emphasis on the vertical NPN transistor, because the NPN transistor is a key element for the high speed operation. Accordingly, the PNP transistor is given a lateral transistors structure which is poor in operational characteristics.
The lateral PNP transistor is constructed with an N type epitaxial layer as a base region, P.sup.+ type emitter and collector regions diffused on the surface of the N type epitaxial layer in such a manner that the P.sup.+ type collector region surrounds the P.sup.+ type emitter region.
The base width which governs the operating speed of a lateral PNP transistor, is determined by the distance between the emitter and collector regions. The emitter junction area which governs the current capacity of the lateral transistor is determined by the product of the peripheral length of the emitter and the emitter diffusion depth.
However, the prior art Bi-CMOS integrated circuit has been unable to achieve a high speed operation and a large current drive to the extent expected.